1. Field of the Invention
Generally, the present disclosure relates to the manufacturing of sophisticated semiconductor devices, and, more specifically, to various methods of forming a semiconductor device with recessed source/drain regions, and a semiconductor device that includes such regions.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPU's, storage devices, ASIC's (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements in a given chip area according to a specified circuit layout, wherein field effect transistors (NMOS and PMOS transistors) represent one important type of circuit elements that substantially determine performance of the integrated circuits. During the fabrication of complex integrated circuits using, for instance, MOS technology, millions of transistors, e.g., NMOS transistors and/or PMOS transistors are formed on a substrate including a crystalline semiconductor layer. A field effect transistor, irrespective of whether an NMOS transistor or a PMOS transistor is considered, typically comprises so-called PN junctions that are formed by an interface of highly doped regions, referred to as drain and source regions, with a slightly doped or non-doped region, such as a channel region, disposed between the highly doped regions source/drain regions.
In a field effect transistor, the conductivity of the channel region, i.e., the drive current capability of the conductive channel is controlled by a gate electrode formed adjacent to the channel region and separated therefrom by a thin gate insulation layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends upon, among other things, the dopant concentration, the mobility of the charge carriers and, for a given extension of the channel region in the transistor width direction, the distance between the source and drain regions, which is also referred to as the channel length of the transistor. Hence, in combination with the capability of rapidly creating a conductive channel below the insulating layer upon application of the control voltage to the gate electrode, the conductivity of the channel region substantially affects the performance of MOS transistors. Thus, since the speed of creating the channel, which depends in part on the conductivity of the gate electrode, and the channel resistivity substantially determine the characteristics of the transistor, the scaling of the channel length, and associated therewith the reduction of channel resistivity, are dominant design efforts used to increase the operating speed of the integrated circuits.
The formation of transistors typically involves performing one or more ion implantation processes to form various doped regions in the substrate, such as halo implant region, extension implant regions and deep source/drain implant regions. In many of the cases, one or more sidewall spacers are formed adjacent a gate electrode structure so as to control the location of the various implant regions. Typically, these sidewall spacers are made of silicon nitride to facilitate processing. More specifically, silicon nitride is often selected because it can be readily etched, and thus removed, relative to a silicon substrate and an underlying silicon dioxide liner layer which is frequently present to act as an etch stop layer when the silicon nitride spacer is removed.
FIGS. 1A-1G depict one illustrative prior art process flow for forming a semiconductor device 100 that includes an illustrative PMOS transistor 100P and an illustrative NMOS transistor 100N using an illustrative combination of silicon nitride sidewall spacers. As shown in FIG. 1A, the process begins with the formation of illustrative gate electrode structures 14 for the PMOS transistor 100P and the NMOS transistor 100N in and above regions of the substrate 10 that are separated by an illustrative shallow trench isolation structure 12. The gate electrode structures 14 generally include a gate insulation layer 14A and one or more conductive gate electrode layers 14B. A gate cap layer 16, made of a material such as silicon nitride, is formed above the gate structures 14. Also depicted in FIG. 1A is an illustrative liner layer 18, made of a material such as silicon dioxide having a thickness of approximately 3-5 nm, that is conformally deposited on the device 100. The gate electrode structures 14 depicted herein are intended to be schematic and representative in nature, as the materials of construction used in the gate structures 14 may be different for the PMOS transistor 100P as compared to the NMOS transistor 100N, e.g., the PMOS transistor 100P may have multiple layers of conductive metal, etc. The gate insulation layer 14A may be comprised of a variety of materials, such as silicon dioxide, silicon oxynitride, a high-k (k value greater than 10) insulating material. The gate electrode layer 14B may be comprised of one or more layers of conductive materials, such as polysilicon, a metal, etc. The structure depicted in FIG. 1A may be formed by a performing a variety of know techniques. For example, the layers of material that make up the gate insulation layer 14A, the gate electrode layer 14B and the gate cap layer 16 may be blanket-deposited above the substrate 10 and, thereafter, one or more etching process are performed through a patterned mask layer (not shown) to define the basic structures depicted in FIG. 1A. Thereafter, a conformal deposition process is performed to form the liner layer 18.
FIG. 1B depicts the device 100 after several process operations have been performed. More specifically, illustrative silicon nitride sidewall spacers 20 with an illustrative base width of about 5-10 nm are formed adjacent the liner layer 18 for both the PMOS transistor 100P and the NMOS transistor 100N. The spacers 20 may be formed by depositing a layer of spacer material and thereafter performing anisotropic etching process. Exposed horizontal portions of the oxide liner layer 18 are removed after the spacers are formed. Next, a masking layer (not shown), e.g., such a photoresist mask, is formed so as to cover the NMOS transistor 100N and expose the PMOS transistor 100P for further processing. Then, one or more ion implantation processes are performed on the exposed PMOS transistor 100P to form various doped regions in the substrate 10, although such doped regions are not depicted in the drawing for purposes of clarity. More specifically, at the point depicted in FIG. 1B, an ion implant process may be performed using an N-type dopant material to form so-called halo implant regions in the substrate 10 for the PMOS transistor 100P, and another ion implant process may be performed using a P-type dopant material to form extension implant regions for the PMOS transistor 100P. Thereafter, a very quick anneal process, such as a laser anneal process, may be performed at a temperature of about 1250° C. for about 10 milliseconds or so to repair the damaged lattice structure of the substrate 10 in the areas that were subjected to the ion implant processes discussed above.
FIG. 1C also depicts the device 100 after several process operations have been performed on the device 100. More specifically, a hard mask layer 21, made of a material such as silicon nitride, is formed above the NMOS transistor 100N. The hard mask layer 21 may be formed by blanket-depositing the hard mask layer 21 across the device 100 and, thereafter, forming a masking layer (not shown), e.g., such a photoresist mask so as to cover the NMOS transistor 100N and expose the PMOS transistor 100P for further processing. Then an etching process is performed to remove the hard mask layer 21 from above the PMOS transistor 100P. Thereafter, a second sidewall spacer 22 made of, for example, silicon nitride, is formed adjacent sidewall spacer 20 on the PMOS transistor 100P. The spacer 22 may be formed by depositing a layer of spacer material and thereafter performing an anisotropic etching process. In some embodiments, the spacer 22 may have a base width of about 4-8 nm. Next, one or more etching processes are performed to define cavities 24 in areas of substrate 10 where source/drain regions for the PMOS transistor 100P will ultimately be formed. The depth and shape of the cavities 24 may vary depending upon the particular application. In one example, where the cavities 24 have an overall depth 25 of about 70 nm, the cavities 24 may be formed by performing an initial dry anisotropic etching process to a depth of about 40-50 nm and thereafter, performing a wet etching process using, for example TMAH, which has an etch rate that varies based upon the crystalline structure of the substrate 10, e.g., the etching process using TMAH exhibits a higher etch rate in the 110 direction than it does in the 100 direction.
FIG. 1D depicts the device 100 after an epitaxial deposition process is performed to form epitaxial silicon germanium regions 26 in the cavities 24. In the depicted example, the regions 26 have an overfill portion that extends above the surface 10S of the substrate 10. In the depicted example, the uppermost surface of the epitaxial silicon germanium regions 26 extends above the substrate 10 by a distance 27 of about 25 nm. The regions 26 may be formed by performing well know epitaxial deposition processes. The device 100 in FIG. 1D has also be subjected to an etching process using, for example, hot phosphoric acid, to remove all of the exposed nitride materials, such as the hard mask layer 21, the sidewall spacers 20, the sidewall spacers 22 and the gate cape layer 16.
As shown in FIG. 1E, the original liner layer 18 may remain in place. Alternatively, the original liner layer 18 may be removed and new liner layer comprised of, for example, 3-5 nm of silicon dioxide, may be formed it its place. Thereafter, illustrative silicon nitride sidewall spacers 28 with an illustrative base width of about 5-10 nm are formed adjacent the liner layer 18 for both the PMOS transistor 100P and the NMOS transistor 100N. The spacers 28 may be formed by depositing a layer of spacer material and thereafter performing an anisotropic etching process. Next, a masking layer (not shown), e.g., such a photoresist mask, is formed so as to cover the PMOS transistor 100P and expose the NMOS transistor 100N for further processing. Then, one or more ion implantation processes are performed on the exposed NMOS transistor 100N to form various doped regions in the substrate 10, although such doped regions are not depicted in the drawing for purposes of clarity. More specifically, at the point depicted in FIG. 1E, an ion implant process may be performed using an P-type dopant material to form so-called halo implant regions in the substrate 10 for the NMOS transistor 100N, and another ion implant process may be performed using a N-type dopant material to form extension implant regions for the NMOS transistor 100N. Thereafter, a very quick anneal process, such as a laser anneal process, may be performed at a temperature of about 1250° C. for about 10 milliseconds or so to repair the damaged lattice structure of the substrate 10 in the areas that were subjected to the ion implant processes discussed above.
Next, as shown in FIG. 1F, silicon nitride sidewall spacers 30 are formed form both the PMOS transistor 100P and the NMOS transistor 100N. Although not depicted in the drawings, another conformal liner layer of, for example, 3-5 nm of silicon dioxide, may be formed so as to cover the spacers 28 prior to forming the spacers 30. Thereafter, deep source/drain ion implant processes are performed on the PMOS transistor 100P and the NMOS transistor 100N using appropriate masking layers and appropriate dopant materials, all of which are well known to those skilled in the art, to form source/drain implant regions (not shown) in the substrate 10. One or more anneal processes are then performed to repair lattice damage to the substrate and to activate the implanted dopant material.
FIG. 1G depicts the device 100 after metal silicide regions 32 have been formed on the device 100. The metal silicide regions 32 may be made of any metal silicide and they may be formed using traditional silicidation techniques. The metal silicide regions 32 need not be the same metal silicide material on both the PMOS transistor 100P and the NMOS transistor 100N, although that may be the case. Although not depicted in the drawings, the fabrication of the device 100 would include several additional steps such as the formation of a plurality of conductive contacts or plugs in a layer of insulating material so as to establish electrical connection with the source/drain regions of the transistors.
In a basic transistor, there are one or more conductive contact plugs that are used for electrical connection to the source/drain regions of the transistor. This arrangement creates an undesirable capacitor (two conductors separated by a dielectric material) between the gate electrode and the conductive contact plugs. This undesirable fringe capacitor must be charged and discharged every switching cycle of the transistor. In many cases, this dielectric material consists of the silicon nitride spacers discussed above that are used in forming the various doped regions for the transistors, i.e., the extension regions and source/drain regions. One problem with the aforementioned use of silicon nitride spacers is that they have a significantly higher dielectric constant (k of about 6.7) as compared to, for example, silicon dioxide (k of about 3.9). As a result of the foregoing, the use of silicon nitride spacers tends to deteriorate the dynamic switching speed of the transistor as the current used to charge/uncharge the fringe capacitor is not available for current transportation. Such problems may result in a circuit exhibiting longer rise/fall times for a given switching cycle. This problem may be even more problematic for a PMOS transistor 100P given the amount of the overfill of the epitaxial silicon germanium regions 26 which tends to create areas where more silicon nitride material can accumulate as compared to an NMOS transistor.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.